The present invention relates to magnetic integrated circuit structure suitable for use in magnetic semiconductor memories.
Computer memory technology has experienced profound advances in the course of the last two decades. An early enabling computer memory technology was magnetic core memory technology. To form magnetic core memories, seemingly innumerable miniature ferrite cores, toroid-shaped, were painstakingly interwoven within a fine matrix of wires, three or more wires passing through the center of each core. By applying a magnetizing current, each core could be placed in one of two different magnetic states, representing a logic 1 and a logic 0, respectively. A coincident current technique was used to select particular cores for the reading and writing of data. Core memory is non-volatile, meaning that data remains unchanged over power cycles: power can be removed from the memory and later reapplied without changing the contents of the memory. Core memory is also xe2x80x9cradiation-hard,xe2x80x9d i.e., unaffected in its operation by ionizing radiation such as gamma rays. Nevertheless, by and large, because of the labor-intensive nature of core memory manufacture and its size, core memory has long been abandoned in favor of semiconductor memory.
Currently the most popular memory technology is MOS DRAM (Metal-Oxide-Semniconductor Dynamic Random Access Memory) technology. In MOS DRAMs. a data bit is stored by injecting charge into or removing charge from a single storage capacitor, through a single transistor. Very dense MOS DRAM chips of up to 256 Mb capacity have been achieved. DRAMs, like MOS devices generally, are low in power consumption. Because leakage occurs from the storage capacitor, however, DRAMs must be refreshed (have the correct charge on each individual storage capacitor restored) at frequent intervals. Furthermore, as compared to core memory which is non-volatile and radiation-hard, DRAM is neither. The need for non-volatile memory and rapid-access memory therefore requires the use of memory hierarchies including multiple different types of memory, i.e., both non-volatile memory (such as FLASH, EEPROM, Ferroelectric memory, EPROM disk, tape, etc.) and volatile memory (such as DRAM, SRAM, etc.). Flash, EEPROM and Ferroelectric memory types provide non-volatility but have a limited number of write cycles before wear-out and in general the write cycle is substantially slower than the read cycle. Memory hierarchies in turn require memory I/O architectures of varying degrees of sophistication. In the case of personal computers, starting up, or xe2x80x9cbootingxe2x80x9d the computer can take a considerable amount of time as a consequence of the need to transfer information from non-volatile to volatile memory.
Clearly, a non-volatile semiconductor memory comparable to DRAM in terms of density, power consumption and write cycle speed is much to be desired. Several memory structures have been proposed to this end, as exemplified by U.S. Pat. Nos. 5,329,480, 5,295,097, 5,068,826, 4,887,236, 4,803,658, and 3,727,199, among others. Unfortunately, efforts to perfect such magnetic semiconductor memories have been largely unsuccessful. One impediment has been the low sensitivity of prior-art magnetic field sensing devices and the inability to make small integratable permanent magnets. A well-known sensing mechanism is that of carrier deflection, using a device known as a xe2x80x9cmagFET,xe2x80x9d for example. A magFET is a Field Effect Transistor (FET) having a single source and two or more drains. A magnetic field, when present in the channel region of the device, can deflect carriers away from one of the drains and toward the other drain(s), depending on the strength and direction of the magnetic field.
More particularly, charge carriers passing through a magnetic field experience a force known as the Lorentz force that tends to deflect the carriers according to the direction of the magnetic field. The Lorentz force (F) experienced by a charged carrier is given by the vector equation F=qvxc3x97B, where q is the charge of the carrier, v is the velocity of the carrier and B is the magnetic field through which the carrier is passing (v and B being tensor quantities). (See, for example, C. S. Roumenin, Handbook of Sensors and Actuators, Volume 2, Section 1.3). The Lorentz force, and hence carrier deflection, is maximized when the magnetic field is substantially orthogonal to the direction of carrier travel. In general, the prior art falls far short of achieving an orthogonal field of sufficient magnitude to allow an integrated sensor to generate a detectable signal.
Other shortcomings of proposed prior-art magnetic semiconductor memories also appear. In order to compete successfully with DRAM, a magnetic semiconductor memory bit cell (after giving effect to the gain provided by additional turns in the magnetic structure) should require no more magnetizing current through its permanent magnet structure of several turns than is available from a single, small-size MOS device, which is usually on the order of 2 milliamps or less. Furthermore, the magnetics of such a cell must be sufficiently well-behaved as to not adversely affect adjacent cells in a memory array. In general, the prior art has been unable to provide a magnetic semiconductor element that satisfies all commercial requisites.
The present invention, generally speaking, provides a magnetic memory element that is single domain in nature and has a geometry that mitigates the effects of half-select noise. In a preferred embodiment, the magnetic memory element takes the form of a magnetic post or tube having an aspect ratio in the range of 2:1 (more preferably 4:1). The outside diameter of the magnetic tube or post is preferably less than 0.8 microns, more preferably 0.6 microns or less. The magnetic post or tube then functions as a single magnetic domain. In the case of a magnetic tube, the skin of the tube is formed of a magnetic material and the interior of the tube is formed of a non-magnetic material. Suitable non-magnetic materials include copper, gold and silicon. The coercivity of the magnetic tube structure may be adjusted by adjusting the thickness of the magnetic skin. As a result, the magnetic memory element is readily scalable to smaller geometries as lithographic techniques improve. The combination of very small, single-domain size and a relatively large aspect ratio results in uniquely desirable properties. Current levels within any reasonable expectation operate to switch the state of the magnetic tube only when the magnetic tube is destabilized by running current through it. With currerit flowing through the magnetic tube, its state may be readily changed by running modest currents in opposite directions through two parallel conductors, one on each side of the magnetic tube. When the magnetic tube is switched, the single domain nature of the magnetic tube produces a signal that is typically 5-15 times stronger than signals produced by conventional magnetic memory elements. The magnetic tube functions as a vertical magnetic field generator and may be formed in intimate proximity to a magnetic field sensor such as above the gate of a magFET.